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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16431A
1/2, 1/3, 1/4-DUTY LCD CONTROLLER/DRIVER
The PD16431A is an LCD controller/driver that enables display of segment type LCDs of 1/2, 1/3, or 1/4 duty cycle. This controller/driver has 56 segment output lines of which eight can also be used as LED output lines. Because the LCD driver contained in the PD16431A has separate logic and power supply, up to 6.5 V of LCD drive voltage can be set. In addition, key source output lines for key scanning and key input data lines are also provided, so that the PD16431A is ideal for applications in the front panel of an automobile stereo system.
FEATURES
* Various display modes 1/2 duty: 112 segment outputs or 96 segment outputs + 8 LED outputs 1/3 duty: 168 segment outputs or 144 segment outputs + 8 LED outputs 1/4 duty: 224 segment outputs or 192 segment outputs + 8 LED outputs * Key scan circuit (key source outputs are shared with LCD driver outputs) * Independent LCD driver power supply VLCD (can be set to VDD to 6.5 V) * Serial data input/output (SCK, STB, DATA) * On-chip oscillator incorporated * Power-ON reset circuit
ORDERING INFORMATION
Part Number Package 80-pin plastic QFP (0.65 pitch, 14 x 14)
PD16431AGC-7ET
Document No. IC-3414 (O.D. No. IC-8885) Date Published January 1995 P Printed in Japan
(c)
1995
PD16431A
BLOCK DIAGRAM
S48 S49/LED1
S56/LED8
S1/KS1 S1/KS2
S8/KS8
COM1
48 8 Segment driver 56 Level shifter (56) 56 Key counter Selector circuit 56 Write address STB 56 DATA CLK I/O control 56-bit shift register Output latch (56 x 4) 2 OE
8 LED driver Common driver 4 Level shifter 4
COM4
OE LCD/LED SYNC
Timing generator
Read address OSC
OSCIN
OSCOUT 8-bit shift register 8 KEY REQ Command decoder key1 Key counter Key latch S/R key4
VDD VSS VLCD VLC1 VLC2 VLC3
2
PD16431A
PIN CONFIGURATION
SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49/LED1 SEG50/LED2 SEG51/LED3 SEG52/LED4 SEG53/LED5 SEG54/LED6 SEG55/LED7 SEG56/LED8
61
SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17
60 41 40
80 1
21 20
SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8/KS8 SEG7/KS7 SEG6/KS6 SEG5/KS5 SEG4/KS4 SEG3/KS3 SEG2/KS2 SEG1/KS1 COM4 COM3 COM2 COM1
Note Though VSS and VEE are internally connected, be sure to connect all the power supply pins (VDD, VSS, VLCD, and VEE).
VSS KEY1 KEY2 KEY3 KEY4 KEY REQ SCK DATA STB LCD/LED OE OSCIN OSCOUT SYNC VDD VLCD VLC1 VLC2 VLC3 VEE
3
PD16431A
PIN FUNCTIONS
Symbol SEG1/KS1 to SEG8/KS8 SEG9 to SEG48 SEG49/LED1 to SEG56/LED8 COM1 to COM4 SCK Name Segment output/key source output Segment output Segment output/LED output pins Common output Shift clock input No. 25 to 32 Description These pins serve as LCD segment output pins and key source output pins for key scanning. LCD segment output pins These pins can be used as LCD segment output or LED output pins depending on the setting of the LCD/LED pin. LCD common output pins Data shift clock. Data is read at the rising edge, and is output at the falling edge of this clock. This pin inputs a command or display data, or outputs key data. A command or data is input at the rising edge of the shift clock, starting from the most significant bit. Key data is output at the falling edge of the shift clock, starting from the most significant bit. This pin serves as an open-drain pin in the output mode. Data can be input when this signal goes low. When it goes high, command processing is performed. When this signal goes high, the SEGn/LEDm pins function as LCD segment output pins; when it goes low, they function as LED driver output pins. The LED driver has a drive capability of 15 mA and is N-ch open drain. When this signal goes low, all the segment output and LED output pins are off (SEGn = COMn = VLCD). Internal data are saved. OSCIN OSCOUT SYNC Oscillation input Oscillation output Synchronizing signal 12 13 14 A synchronizing signal input pin. When two or more PD16431A's are used, each device is wired-ORed. This pin must be pulled up when this chip is used alone. KEY1 to KEY4 KEY REQ Key data input Key request output 2 to 5 6 Key data input pins for key scanning This signal goes high when a key is pressed (key data = H). Read the key data only while this pin is high. Power supply pin for internal logic GND pin for internal logic and LED output Power supply pin for LCD drive GND pin for LCD drive Power supply for driving dot matrix LCD Connect a resistor for oscillation circuit across these pins.
33 to 72 73 to 80
21 to 24 7
DATA
Data input/output
8
STB
Strobe input
9
LCD/LED
LCD/LED select
10
OE
Note
Output enable input
11
VDD VSS VLCD VEE VLC1 to VLC3
Logic power supply Logic GND LCD drive power supply LCD GND Power supply for LCD drive
15 1 16 20 17 to 19
Note At OE = L, the key data cannot be written correctly, even when the display ON/OFF of the status command is set to the "normal operation" (10). Also, in this state, unnecessary waveforms are generated from between SEG1/KS1 to SEG8/KS8 during the key scanning period. (The display is OFF.)
4
PD16431A
CONFIGURATION OF SHIFT REGISTER Two shift registers, an 8-bit command register and a 56-bit display register, are provided. The first 8 bits of input data are recognized as a command and are sent to the command register, and the 9th bit and those that follow are recognized as display data and are sent to the display register.
8-bit shift register MSB b7 b0 LSB
Command 56-bit shift register MSB SEG56/LED8 Display data (LCD, LED) SEG1 Transfer direction LSB
The meaning of the display data is as follows: LCD: 0 off, 1 on LED: 0 on, 1 off Be sure to transfer 56 bits of display data. CONFIGURATION OF OUTPUT LATCH
MSB SEG56/LED8 SEG56/LED8 SEG56/LED8 SEG56/LED8 LSB SEG1 SEG1 SEG1 SEG1 COM1 (latch addressNote: 00) COM2 (latch addressNote: 01) COM3 (latch addressNote: 10) COM4 (latch addressNote: 11)
Note Bits b3 and b4 of status command (Refer to page 8.)
5
PD16431A
KEY MATRIX CONFIGURATION An example of key matrix configurations is shown below. 1) When pressing three or more times is assumed: A configuration example is shown below. recognized. In this configuration, 0 to 32 ON switches can be
KEY1 = KEY2 KEY3 KEY4 KS1 KS2 KS3 KS4 KS5 KS6 KS7 KS8
C
2) When pressing twice or more times is assumed: A configuration example is shown below. In this configuration, 0 to 2 ON switches can be recognized.
KEY1 = KEY2 KEY3 KEY4 Diode A KS1 KS2 KS3 KS4 KS5 KS6 KS7 KS8
In this configuration, pressing three or more times may cause OFF switches to be determined to be ON. For example, if SW2 to SW4 are ON and KS1 has been selected (high level) as shown below, SW3 in which current I1 is running is supposed to be detected to be ON. However, since SW2 and SW4 are ON, current I2 runs thus resulting in SW1 to be recognized as being ON.
SW1
SW2
KEY1 I2 KEY2 I1 KEY3 KEY4
SW3 SW4
=
KS1 Select
KS2
KS3
KS4
KS5
KS6
KS7
KS8
6
PD16431A
If diode A is not available, not only the key data may not be read normally but the LCD display may be affected or ICs may be damaged or deteriorated. For example, if SW1 and SW2 are ON and KS1 has been selected (high level) as shown below, this will cause not only current I1 which is supposed to run but also short-circuited current I2 of KS1 to KS2 to run. It is possible that this will then cause the following three problems: (1)Since the level to KEY2 is not correctly sent, the key data cannot be latched correctly. (2)If KS2 is used as SEG2 as well, the LCD display may be distorted (such as causing unintended segments to light up). (3)Since the short-circuited current (current I2) of KS2 (high level) to KS2 (low level) runs, ICS may be damaged or deteriorated
KEY1
SW1 SW2
=
KEY2 I1 KEY3 KEY4 I2 KS1 KS2 KS3 KS4 KS5 KS6 KS7 KS8
Select (high level)
Non Select (low level)
7
PD16431A
CONFIGURATION OF KEY DATA LATCH The key data is latched as illustrated below and is read by a read command, starting from the most significant bit. Key data is read once a frame and latched when coinciding with the immediadtely preceding data. In other words, it requires at least 2 frames from the time the key is pressed till data is confirmed to be the key data (the key request becoming H).
32-bit latch/SHIFT register MSB KS8 KS7 KS6 KS5 KS4 KS3 KS2 KS1 LSB
KEY4 KEY3 KEY2 KEY1
The key data is 0 when off and 1 when on. KEY INPUT EQUIVALENT CIRCUIT
To key latch
KEY n
Pull-down control signal
* The pull-down control signal goes high only during key source output and turns on the pull-down transistor. * The on-resistance of the pull-down transistor is several k.
8
PD16431A
COMMAND A command sets a display mode and a status. The first 1 byte input after the STB pin has fallen is regarded as a command. If the STB pin is made low while a command/data is transferred, serial communication is initialized, and the command/data being transferred is made invalid (the command/data that has been already transferred remains valid, however). (1) Display setting command This command initializes the PD16431A and sets a duty cycle, frame frequency, drive voltage supply method, test mode, and whether the PD16431A operates as the master or a slave. When this command is executed, display is forcibly turned off and key scanning is stopped. To resume the display, the normal operation of the "status command" must be executed. Note, however, that nothing is executed if the same mode is selected.
MSB 0 LSB b6 b5 b4 b3 b2 b1 b0
Sets duty. 00: 1/4 duty, 1/3 bias 01: 1/3 duty, 1/3 bias 10: 1/2 duty, 1/2 bias 11: 1/2 duty, 1/2 bias Sets frame frequency. 00: (fOSC/128) x n 01: (fOSC/256) x n 10: (fOSC/512) x n 11: (fOSC/1024) x n n= duty (1/2, 1/3, 1/4) Sets drive voltage supply method. 0: Internal 1: External Sets master or slave. 0: Master 1: Slave Sets test mode. 0: Normal operation 1: Test mode
Values when power is applied 0 0 0 0 0 0 0
9
PD16431A
(2) Status command This command sets a data write/read mode, turns on/off display, and sets a latch address.
MSB 1 x x LSB b4 b3 b2 b1 b0 x : Don't Care
Sets data write/read mode. 0: Writes display data to output latch 1: Reads key data Turns on/off display 00: Forcibly turns off display (all segments and LEDs off). Stops key scanning. 01: Prohibited 10: Normal operation 11: Don't care Sets latch address. 00: COM1 01: COM2 10: COM3 11: COM4
Values when power is applied x x 0 0 0 0 0
10
PD16431A
OUTPUT SELECT VOLTAGE 1. COM
+ When selected VLCD VLCD 1/2 VLCD VLC2 1/2 VLCD VLC2 VLCD VLCD 1/3 VLCD VLC3 1/2 VLCD VLC2 - GND GND 1/2 VLCD VLC2 1/2 VLCD VLC2 GND GND 2/3 VLCD VLC1 1/2 VLCD VLC2 1/3 bias Bias 1/2 bias
Top
: with internal power supply
Bottom: with external power supply
When not selected
When key scanned
When selected
When not selected
When key scanned
2. SEG
+ When selected GND GND VLCD VLCD GND GND VLCD VLCD GND GND When not selected 2/3 VLCD VLC1 GND GND VLCD VLCD VLCD VLCD GND GND VLCD VLCD GND GND VLCD VLCD 1/3 VLCD VLC3 VLCD VLCD GND GND 1/3 bias - Bias 1/2 bias
When not selected
When key scanned
When key not scanned When selected
When key scanned
When key not scanned
11
PD16431A
OUTPUT WAVEFORM (1) 1/2 duty (1/2 dias)
* K 0 VLCD COM1 VLC2 VEE VLCD COM2 VLC2 VEE VLCD SEG1 VLC2 VEE VLCD SEG9 VLC2 VEE
0
* K 1
1
* K 0
0
* K 1
1
* K 0 *: key scan period (16/fc)
VLCD 1/2VLCD SEG1-COM1 0 -1/2VLCD -VLCD VLCD 1/2VLCD SEG1-COM2 0 -1/2VLCD -VLCD
1 KEY REQ (w/key) 2 KEY REQ (w/keyw/o key) 3 KEY REQ (w/o keyw/key)
12
PD16431A
KEY SCAN PERIOD (K0) EXPANSION
1
K0
0
1 VLCD COM1 VLC2 VEE VLCD SEG1 VLC2 VEE VLCD SEG2 VLC2 VEE VLCD SEG3 VLC2 VEE VLCD SEG4 VLC2 VEE VLCD SEG5-SEG40 VLC2 VEE
2
3
4
5
6
7
8
= Key source output
13
PD16431A
KEY SCAN PERIOD (K1) EXPANSION
0
K1
1
1 VLCD COM1 VLC2 VEE VLCD SEG1-SEG4, SEG9-SEG40 VLC2 VEE VLCD SEG5 VLC2 VEE VLCD SEG6 VLC2 VEE VLCD SEG7 VLC2 VEE VLCD SEG8 VLC2 VEE
2
3
4
5
6
7
8
1 KEY REQ (w/key) 2 KEY REQ (w/keyw/o key) 3 KEY REQ (w/o keyw/key)
= Key source output
14
PD16431A
(2) 1/3 duty (1/3 bias)
* K 0 VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD 1/2VLCD 1/3VLCD 0 SEG1-COM1 -1/3VLCD -1/2VLCD -VLCD VLCD 1/2VLCD 1/3VLCD 0 SEG1-COM2 -1/3VLCD -1/2VLCD -VLCD
0
* K 1
1
* K 2
2
* K 0
0
* K 1
*: key scan period (16/fc)
COM1
COM2
COM3
SEG1
SEG9
15
PD16431A
KEY SCAN PERIOD (K0) EXPANSION
2
K0
0
1 VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE
2
3
4
5
6
7
8
COM1
SEG1
SEG2
SEG3
SEG4
SEG5-SEG8
= Key source output
16
PD16431A
KEY SCAN PERIOD (K1) EXPANSION
0
K1
1
1 VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE
2
3
4
5
6
7
8
COM1
SEG1-SEG4, SEG9-SEG40
SEG5
SEG6
SEG7
SEG8
= Key source output
17
PD16431A
KEY SCAN PERIOD (K2) EXPANSION
1
K2
2
1 VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE
2
3
4
5
6
7
8
COM1
SEG1-SEG40
18
PD16431A
(3) 1/4 duty (1/3 bias)
* K 0 VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE
0
* K 1
1
* K 2
2
* K 3
3
* K 0
0
* K 1
*: key scan period (16/fc)
COM1
COM2
COM3
COM4
SEG1
SEG9
VLCD 2/3VLCD 1/2VLCD 1/3VLCD 0 SEG1-COM1 -1/3VLCD -1/2VLCD -2/3VLCD -VLCD VLCD 2/3VLCD 1/2VLCD 1/3VLCD 0 SEG1-COM2 -1/3VLCD -1/2VLCD -2/3VLCD -VLCD
19
PD16431A
KEY SCAN PERIOD (K0) EXPANSION
3
K0
0
1 VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE
2
3
4
5
6
7
8
COM1
SEG1
SEG2
SEG3
SEG4
SEG5-SEG40
= Key source output
20
PD16431A
KEY SCAN PERIOD (K1) EXPANSION
0
K1
1
1 VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE
2
3
4
5
6
7
8
COM1
SEG1-SEG4, SEG9-SEG40
SEG5
SEG6
SEG7
SEG8
= Key source output
21
PD16431A
KEY SCAN PERIOD (K2) EXPANSION
1
K2
2
1 VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE
2
3
4
5
6
7
8
COM1
SEG1-SEG40
KEY SCAN PERIOD (K3) EXPANSION
2
K3
3
1 VLCD VLC1 VLC2 VLC3 VEE VLCD VLC1 VLC2 VLC3 VEE
2
3
4
5
6
7
8
COM1
SEG1-SEG40
22
PD16431A
SERIAL COMMUNICATION FORMAT (1) Receive (command/data write)
If data continues STB
DATA
b7
b6
b5
b2
b1
b0
SCK
1
2
3
6
7
8
(2) Transmit (command/data read)
STB
DATA
7
6
5
2
1
0
7
6
5
4
3
SCK
1
2
3
6
7
8 1 s
1
2
3
4
5
6
Data read command set
Wait time tWAIT
Data read
Note Because the DATA pin is an N-ch open-drain output pin, be sure to connect an external pull-up resistor to this pin (1 k to 10 k).
23
PD16431A
APPLICATION 1. Example of initial setting + display data write
Command/data Parameter Start Set display command STB b7 b6 b5 b4 b3 b2 b1 b0 H L 00000000 1/4 duty, frame frequency = fosc/128 x 1/4, internal drive voltage, master H Status command Display data 1 L L 10000000 xxxxxxxx Display data write, display off, latch address: COM1 Remarks
Display data 7
L H
xxxxxxxx

COM1 data (7 bytes)
Status command Display data 1
L L
10001000 xxxxxxxx
Display data write, display off, latch address: COM2
Display data 7
L H
xxxxxxxx

COM2 data (7 bytes)
Status command Display data 1
L L
10010000 xxxxxxxx
Display data write, display off, latch address: COM3
Display data 7
L H
xxxxxxxx

COM3 data (7 bytes)
Status command Display data 1
L L
10011000 xxxxxxxx
Display data write, display off, latch address: COM4
Display data 7
L H
xxxxxxxx

COM4 data (7 bytes)
Status command End
L H
10000100
Display data write, display on
24
PD16431A
2. Example of display data write (rewrite, 1/4)
Command/data Parameter Start Status command Display data 1 STB b7 b6 b5 b4 b3 b2 b1 b0 H L L 10000100 xxxxxxxx Display data write, display on, latch address: COM1 Remarks
Display data 7
L H
xxxxxxxx
COM1 data (7 bytes)
Status command Display data 1
L L
10001100 xxxxxxxx
Display data write, display on, latch address: COM2
Display data 7
L H
xxxxxxxx
COM2 data (7 bytes)
Status command Display data 1
L L
10010100 xxxxxxxx
Display data write, display on, latch address: COM3
Display data 7
L H
xxxxxxxx
COM3 data (7 bytes)
Status command Display data 1
L L
10011100 xxxxxxxx
Display data write, display on, latch address: COM4
Display data 7 End
L H
xxxxxxxx
COM4 data (7 bytes)
25
PD16431A
3. Example of key data read
Command/data Parameter KEY REQ check STB b7 b6 b5 b4 b3 b2 b1 b0 KEY REQ = H: Key data exists. Start reading. Remarks
KEY REQ = L: Key data does not exist (reading is inhibited). Check KEY REQ again.
Start Status command Wait time Key data 1
H L L L xxxxxxxx 10000101 Data read, display on 1 s
Key data 4 End
L H
xxxxxxxx
4 bytes
26
PD16431A
ABSOLUTE MAXIMUM RATINGS (Ta = 25 C, VSS = 0 V)
Parameter Logic supply voltage Logic input voltage Logic output voltage (DATA) LCD drive supply voltage Symbol VDD VIN VOUT VLCD Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to +7.0 -0.3 to +7.0 -0.3 to VLCD + 0.3 -0.3 to VLCD + 0.3 Unit V V V V V V
LCD drive supply input voltage VLC1 to VLC3 Driver output voltage (segment, common, LED) LED output current Operating ambient temperature Storage temperature Permissible package power dissipation VOUT2
IO Topt Tstg PT
+20 -40 to +85 -55 to +150 1 000
mA C C mW
RECOMMENDED OPERATING CONDITIONS
Parameter Logic supply voltage LCD drive supply voltage Logic input voltage Driver output voltage Symbol VDD VLCD VIN VLC1 to VLC3 MIN. 2.7 VDD 0 0 TYP. 5.0 5.0 MAX. 5.5 6.5 VDD VLCD Unit V V V V
27
PD16431A
ELECTRICAL SPECIFICATIONS (Unless otherwise specified, Ta = -40 to +85 C, VDD = VLCD = 5 V 10%)
Parameter Input voltage, high Input voltage, low Input current, high Input current, low Output voltage, low Output voltage, high Output voltage, low Leakage current, high Leakage current, low Common output ON resistance Segment output ON resistance Logic current dissipation LCD drive current consumption Symbol VIH VIL IIH IIL VOL1 VOH2 VOL2 ILOH2 ILOL2 RCOM RSEG IDD ILCD CLK, STB, LCD/LED, OE CLK, STB, LCD/LED, OE LED1 to LED8. IOL1 = 15 mA OSCOUT, IOH2 = -1 mA DATA, OSCOUT, SYNC, IOL2 = 4 mA DATA, SYNC, VIN OUT = VDD DATA, SYNC, VIN OUT = VSS COM1 to COM4, | IO | = 100 A SEG1 to SEG56, | IO | = 100 A fOSC = 250 kHz With internal bias and no load 0.9 VDD 0.1 VDD 1 -1 2.4 4.0 250 500 MIN. 0.7 VDD 0 TYP. MAX. VDD 0.3 VDD 1 -1 1.0 Unit V V
A A
V V V mA mA k k
A A
Remark The TYP. value is a reference value at Ta = 25 C.
28
PD16431A
SWITCHING CHARACTERISTICS (Unless otherwise specified, Ta = -40 to +85 C, VDD = VLCD = 5 V 10%, RL = 5 k, CL = 150 pF)
Parameter Oscillation frequency Oscillation frequency Propagation delay time Propagation delay time SYNC delay time Symbol fOSC fOSC tPZL tPLZ tDSYNC R = 100 k R = 200 k SCK DATA SCK DATA Conditions MIN. 175 105 TYP. 250 150 MAX. 325 195 100 300 1.5 Unit kHz kHz ns ns
s
TIMING REQUIREMENTS (Unless otherwise specified, Ta = -40 to +85 C, VDD = VLCD = 5 V 10%, RL = 5 k, CL = 150 pF)
Parameter Clock frequency High-level clock pulse width Low-level clock pulse width Shift clock cycle High-level shift clock pulse width Low-level shift clock pulse width Shift clock hold time Data setup time Data hold time STB hold time STB pulse width Wait time SYNC removal time tHSTBK tDS tDH tDKSTB tWSTB tWAIT tSREM CLK CLK STB SCK DATA SCK SCK DATA SCK STB 1.5 100 200 1 1 1 250 Symbol fC tWHC tWLC tCYK tWHK Conditions OSCIN external clock OSCIN external clock OSCIN external clock SCK SCK MIN. 50 1.5 1.5 900 400 TYP. MAX. 325 16 16 Unit kHz
s s
ns ns
tWLK
SCK
400
ns
s
ns ns
s s s
ns
Output Load
VDD
5 k
OUTPUT
150 pF
29
PD16431A
Switching Characteristic Waveform
1/fc tWHC
VIH CSCIN VIL tWLC tWSTB VIH VIL tHKSTB
STB
tCYK tWLK VIH SCK VIL tDS VIH VIL tDH tWHK
DATA
SYNC timing (master) 1 frame fOSC tDSYNC SYNC Internal reset 1 frame
SYNC timing (slave) 1 frame 1 frame
tSREM
30
PD16431A
Switching Characteristic Waveform
SCK VIL tPZL tPLZ
DATA VOL2
Application Circuit Example (with LED, 1/4 duty, 1/3 bias)
LCD
VDD R5 To microcomputer VDD R6 SYNC. OSCIN R7 OSCOUT VDD VSS VLCD VLC1 DATA SCK STB KEY REQ OE LCD/LED
4
8
COMn
40
SEG1/KS1 to SEG8/KS8 SEG9 to SEG48
8 Key matrix 8x4
VLCD R8 LED
PD16431A
LEDn KEYn
8 4 R1 R2 R5, R6 R7 R8 : 1 k to 10 k : 1/2 R1 : 1 k to 10 k : 100 k TYP. : 330 to 1 k
VLC2
VLC3
VEE
R1 +5 V GND +6 V
R2
R2
R1 GND
R1 through R2 are not necessary when the internal drive voltage is selected (VLC1 through VLC3 are open).
31
PD16431A
Note Example of external source circuit (when 1/2 bias)
VDD VSS
VLC0
VLC1
VLC2
VLC3
VEE
R1 +5 V GND +6 V
R1 GND
R1 = 1 k to 10 k (approx.)
The application circuits and their parameters are for references only and are not intended for use in actual design-in's.
32
PD16431A
80 PIN PLASTIC LQFP ( 14)
A B
60 61
41 40
detail of lead end
C
D
S
F
80 1
21 20
G
H
I
M
J K
P
N
NOTE
L
M
ITEM A B C D F G H I J K L M N P Q R S
Q
MILLIMETERS 16.00.2 14.00.1 14.00.1 16.00.2 0.825 0.825 0.300.10 0.13 0.65 (T.P.) 1.00.2 0.50.2 0.125 +0.10 -0.05 0.10 1.40.1 0.1250.075 3 +7 -3 1.7 MAX.
R
INCHES 0.6300.008 0.551 +0.005 -0.004 0.551 +0.005 -0.004 0.6300.008 0.032 0.032 0.012 +0.004 -0.005 0.005 0.026 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.005 +0.004 -0.002 0.004 0.0550.004 0.0050.003 3 +7 -3 0.067 MAX. S80GC-65-7ET-1
Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
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PD16431A
REFERENCE
Document Name NEC Semiconductor Device Reliability/Quality Control System Quality grade on NEC Semiconductor Devices Document No. IEI-1212 IEI-1209
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product.
M4 94.11
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